1. Field of the Invention
This invention relates generally to minicomputing systems and particularly to a priority resolver mechanism for resolving conflicts between the minicomputing subsystems vying for access to a shared resource and more particularly to cache memory.
2. Description of Prior Art
The storage hierarchy concept is based on the phenomenon that programs under execution exhibit the behavior that in a given period of time a localized area of memory receives a very high frequency usage. Thus, a memory organization that provides a relatively small size buffer (cache memory) at the CPU interface and various levels of increasing capacity slower storage can provide an effective access time that lies somewhere in the range between the fastest and slowest elements of the hierarchy.
There are various means of communication between the various, subsystems and cache memory. In such communication, conflict may result and a priority resolving mechanism is necessary to resolve the conflict. There are a variety of priority resolvers in the prior art, one typical such priority mechanism being utilized in the system disclosed in U.S. Pat. No. 4,030,075 issued June 14, 1977 and entitled "Data Processing System Having Distributed Priority Network" incorporated herein by reference.
Generally, priority resolvers inherently have a metastable property resulting from the violation of set-up time, hold time and pulse width specifications which may result in failure to resolve in a predictable period of time. When these specified minimum times are violated, there can be exactly enough energy in the input signal to precisely balance the input and output voltages of the latching circuit. Less energy will not precisely balance the input and output voltages and will allow the latch to settle back into its original state. Likewise, more energy will cause the latch to achieve the new state. Therefore, an extremely small window of time exists which will cause a very long indeterminate state at the output. Recovery from this state is dependent upon available internal imbalanced charging currents and node capacitance. These parameters are both process dependent; therefore, recovery time of a particular part is both vendor and batch dependent. What is needed is an improved priority resolver that eliminates this timing uncertainty.
Typical U.S. patents, although not necessarily the closest prior art relating to priority resolving devices, are U.S. Pat. No. 3,993,981 entitled "Apparatus for Providing Data Transfer Requests in a Data Processing System"; U.S. Pat. No. 4,001,783 entitled "Priority Interrupt Mechanism"; U.S. Pat. No. 4,225,942 entitled "Daisy Chaining of Device Interrupts in a Cathode Ray Tube Device"; and U.S. Pat. No. 4,385,382 entitled "Communication Multiplexer Having a Variable Priority Scheme Using a Read Only Memory".